1. Technical Field
Embodiments of the present disclosure may generally relate to a semiconductor device, and more particularly to a technology regarding cell reliability of a semiconductor memory device.
2. Related Art
A semiconductor memory device is a memory device capable of storing data therein and reading the stored data.
Semiconductor memory devices are generally classified into a Random Access Memory (RAM) and a Read Only Memory (ROM). Data stored in the RAM is lost when the power supply is no longer supplied, and a memory configured to store the above-mentioned data therein is referred to as a volatile memory. Data stored in the ROM is not lost even when the power supply is no longer supplied, and a memory capable of storing the above-mentioned data is referred to as a non-volatile memory.
Generally, semiconductor memory devices are classified into a volatile memory device and a non-volatile memory device according to whether or not data is retained when a power source is cut off.
The semiconductor memory device such as a DRAM from among volatile memory devices includes a bit line sense amplifier. After a memory cell accesses the bit line sense amplifier, charge sharing between the memory cell and the bit line is achieved in the bit line sense amplifier. As a result, a small signal difference generated in the bit line is first amplified, such that the bit line sense amplifier is of importance to the semiconductor memory device.
Generally, a bit line structure of the semiconductor memory device is classified into an open bit line structure and a folded bit line structure.
The semiconductor memory device having the open bit line structure includes a bit line extending from the bit line sense amplifier and a complementary bit line (or an inverted bit line) extending opposite to the bit line sense amplifier.
The semiconductor memory device having the folded bit line structure includes a bit line and a complementary bit line which extend from the bit line sense amplifier. In this case, the bit line and the complementary bit line may construct a pair of bit lines. The open bit line structured semiconductor memory device includes many more memory cells than the folded bit line structured semiconductor memory device. Therefore, the open bit line structured semiconductor memory devices have recently been widely used throughout the world.
Operations of the semiconductor memory device will hereinafter be described.
A row strobe signal (/RAS) signal acting as a main signal for operating the DRAM device is activated to a low level, so that at least one row address signal is input to a row address buffer. In this case, a row decoding operation for selecting one of word lines contained in the cell array is carried out by decoding the row address signals.
In this case, the data of cells coupled to the selected word line is applied to the pair of bit lines (BL, /BL) composed of a bit line and its complementary bit line. As a result, a sense-amplifier (also called a sense-amp) enable signal indicating an operation start time of a sense amplifier is enabled to drive a sense-amp driving circuit of a cell block selected by the row address signals.
After that, sense-amp bias potentials are transitioned to a core potential (Vcore) and a ground potential (Vss) by the sense-amp driving circuit, so that the sense amplifier is driven. If the sense amplifier starts operation, voltages of the bit lines (BL, /BL) that have maintained a slight potential difference therebetween are transitioned to have a high potential different therebetween.
Thereafter, a column decoder turns on a column transfer transistor that transfers data from each bit line to data bus lines in response to column address signals, such that data stored in the pair of bit lines (BL, /BL) is output to the outside of the semiconductor memory device through the data bus lines (DB, /DB).